Spiking Neural Networks (SNNs) offer a brain-inspired path toward highly efficient computation, but their practical deployment is constrained by the challenge of managing and executing their massive parallelism on physical hardware. This problem mirrors the historical challenge in processor design of moving beyond serial execution, a barrier broken by superscalar architectures that dispatch multiple instructions to parallel functional units. Drawing inspiration from this paradigm, we introduce a hardware-software co-design framework that treats synaptic events as parallelizable micro-operations. We present SupraSNN, a superscalar-inspired architecture that achieves high synapse-level parallelism by physically decoupling synaptic and neuronal computations. Within this architecture, a Multi-Cast Tree routes spike data to multiple parallel Synapse Processing Units serve as the computational pipelines, while a Merge Tree consolidates distributed results for processing by a unified Neuron Unit--deliberately centralizing complex neuron state dynamics to mitigate hardware overhead and resource duplication. The efficacy of this architecture is enabled by a sophisticated partitioning and scheduling framework that first maps the SNN onto hardware respecting memory constraints, then heuristic scheduling determines the synaptic execution order, maximizing throughput and resource utilization. Implementing a feedforward SNN trained on MNIST (93.44% accuracy), SupraSNN achieves 149 $μs$ inference latency and 0.025 mJ per image (0.276 nJ per synapse) on the Xilinx Zynq XC7Z020 FPGA--delivering 47.6% lower latency and 5.6$\times$ better energy efficiency than prior FPGA-based SNN accelerators. Beyond vision tasks, a recurrent SNN on the Spiking Heidelberg Dataset (71.82% accuracy) achieves 1.41 ms latency and 0.77 mJ per sample on XC7Z030.

翻译：摘要：脉冲神经网络（SNN）提供了一条受大脑启发的、通向高效计算的路径，但其实际部署受限于在物理硬件上管理和执行其大规模并行性的挑战。这个问题类似于处理器设计历史上超越串行执行的挑战，而这一障碍被超标量架构所突破——该架构将多条指令分派到并行功能单元。受此范式启发，我们引入了一种软硬件协同设计框架，将突触事件视为可并行的微操作。我们提出了SupraSNN，一种受超标量启发的架构，通过物理上解耦突触和神经元的计算，实现了高突触级并行性。在该架构中，多播树将脉冲数据路由到多个并行突触处理单元（作为计算流水线），而合并树则汇集分布式结果，交由统一的神经元单元处理——该单元特意集中处理复杂的神经元状态动态，以降低硬件开销和资源重复。这一架构的有效性依赖于一个精细化的划分与调度框架：首先将SNN映射到遵循内存约束的硬件上，然后通过启发式调度确定突触执行顺序，最大化吞吐量和资源利用率。在MNIST上训练的（准确率93.44%）前馈SNN中，SupraSNN在Xilinx Zynq XC7Z020 FPGA上实现了149微秒的推理延迟和每幅图像0.025毫焦（每个突触0.276纳焦）的能耗——相比先前基于FPGA的SNN加速器，延迟降低47.6%，能效提升5.6倍。在视觉任务之外，Spiking Heidelberg数据集上的循环SNN（准确率71.82%）在XC7Z030上实现了每样本1.41毫秒延迟和0.77毫焦能耗。