Demands on Field-Programmable Gate Array (FPGA) data transport have been increasing over the years as frame sizes and refresh rates increase. As the bandwidths requirements increase the ability to implement data transport protocol layers using "soft" programmable logic becomes harder and start to require harden IP blocks implementation. To reduce the number of physical links and interconnects, it is common for data acquisition systems to require interleaving of streams on the same link (e.g. streaming data and streaming register access). This paper presents a way to leverage existing FPGA harden IP blocks to achieve a robust, low latency 100 Gb/s point-to-point link with minimal programmable logic overhead geared towards the needs of data acquisition systems with interleaved streaming requirements.

翻译：多年来,随着框架大小和刷新率的增加,对外地可编程门阵列数据传输的需求不断增加。随着带宽要求提高使用“软”可编程逻辑执行数据传输协议层的能力,并开始要求实施硬化的IP区块。为了减少物理链接和互连,数据采集系统通常要求在同一链接上互连流流(如流数据、流登记存取)。本文介绍了如何利用现有的FPGA硬化IP区块实现一个稳健的、低中值100千磅/秒点对点链接,与最起码的可编程逻辑管理连接,以满足具有互连流要求的数据获取系统的需求。