Recent advances in logic schemes and fabrication processes have renewed interest in using superconductor electronics for energy-efficient computing and quantum control processors. However, scalable superconducting memory still poses a challenge. To address this issue, we present an alternative to approaches that solely emphasize storage cell miniaturization by exploiting the minimal attenuation and dispersion properties of superconducting passive transmission lines to develop a delay-line memory system. This fully superconducting design operates at speeds between 20 GHz and 100 GHz, with $\pm$24\% and $\pm$13\% bias margins, respectively, and demonstrates data densities in the 10s of Mbit/cm$^2$ with the MIT Lincoln Laboratory SC2 fabrication process. Additionally, the circulating nature of this design allows for minimal control circuitry, eliminates the need for data splitting and merging, and enables inexpensive implementations of sequential-access and content-addressable memories. Further advances in fabrication processes suggest data densities of 100s of Mbit/cm$^2$ and beyond.

翻译：逻辑方案与制备工艺的最新进展重新激发了人们对利用超导电子学实现高能效计算与量子控制处理器的兴趣。然而，可扩展的超导存储器仍是一大挑战。为此，我们提出一种替代方案——并非仅专注于存储单元小型化，而是利用超导无源传输线极低的衰减与色散特性，构建延迟线存储系统。这种全超导设计可在20 GHz至100 GHz频率下运行，分别具有±24%与±13%的偏置裕度，并在麻省理工学院林肯实验室SC2制备工艺下实现了数十Mbit/cm²量级的数据密度。此外，该设计的循环特性使其仅需极简控制电路，无需数据拆分与合并，并可低成本实现顺序存取存储器与内容可寻址存储器。随着制备工艺的进一步发展，数据密度有望达到数百Mbit/cm²甚至更高。