Power side-channel (PSC) analysis is pivotal for securing cryptographic hardware. Prior art focused on securing gate-level netlists obtained as-is from chip design automation, neglecting all the complexities and potential side-effects for security arising from the design automation process. That is, automation traditionally prioritizes power, performance, and area (PPA), sidelining security. We propose a "security-first" approach, refining the logic synthesis stage to enhance the overall resilience of PSC countermeasures. We introduce ASCENT, a learning-and-search-based framework that (i) drastically reduces the time for post-design PSC evaluation and (ii) explores the security-vs-PPA design space. Thus, ASCENT enables an efficient exploration of a large number of candidate netlists, leading to an improvement in PSC resilience compared to regular PPA-optimized netlists. ASCENT is up to 120x faster than traditional PSC analysis and yields a 3.11x improvement for PSC resilience of state-of-the-art PSC countermeasures

翻译：功耗侧信道分析对于保障密码硬件安全至关重要。现有研究主要关注从芯片设计自动化流程中直接获取的门级网表的安全性，却忽视了设计自动化过程本身带来的复杂性及其对安全性的潜在副作用。传统自动化流程通常优先考虑功耗、性能与面积指标，而将安全性置于次要地位。本文提出一种“安全优先”的设计方法，通过优化逻辑综合阶段来提升功耗侧信道防护措施的整体抗性。我们提出ASCENT框架，该基于学习与搜索的框架能够：（1）大幅缩短设计后功耗侧信道评估所需时间；（2）系统探索安全性与PPA指标之间的设计空间。因此，ASCENT可实现对大量候选网表的高效探索，相比常规PPA优化网表能显著提升功耗侧信道抗性。实验表明，ASCENT相比传统功耗侧信道分析提速最高达120倍，并将前沿功耗侧信道防护措施的侧信道抗性提升3.11倍。