Whilst Field-Programmable Gate Arrays (FPGAs) have been popular in accelerating high-frequency financial workload for many years, their application in quantitative finance, the utilisation of mathematical models to analyse financial markets and securities, is less mature. Nevertheless, recent work has demonstrated the benefits that FPGAs can deliver to quantitative workloads, and in this paper, we study whether the Versal ACAP and its AI Engines (AIEs) can also deliver improved performance. We focus specifically on the industry standard Strategic Technology Analysis Center's (STAC) derivatives risk analysis benchmark STAC-A2. Porting a purely FPGA-based accelerator STAC-A2 inspired market risk (SIMR) benchmark to the Versal ACAP device by combining Programmable Logic (PL) and AIEs, we explore the development approach and techniques, before comparing performance across PL and AIEs. Ultimately, we found that our AIE approach is slower than a highly optimised existing PL-only version due to limits on both the AIE and PL that we explore and describe.

翻译：尽管现场可编程门阵列（FPGA）多年来在高频金融工作负载加速领域广受欢迎，但其在量化金融（即运用数学模型分析金融市场与证券）中的应用尚不成熟。然而，近期研究已证明FPGA可为量化工作负载带来显著效益。本文针对此背景，探究Versal ACAP及其AI引擎（AIEs）能否进一步提升性能。我们聚焦于行业标准——战略技术分析中心（STAC）的衍生品风险分析基准STAC-A2。通过将基于纯FPGA加速器的STAC-A2衍生市场风险（SIMR）基准移植至Versal ACAP设备，采用可编程逻辑（PL）与AI引擎协同计算的方案，探索开发方法与技术路径，并对比两者性能差异。最终发现：受限于所探讨的AI引擎与PL架构设计约束，本研究的AI引擎方案性能低于高度优化的纯PL实现版本。