Automated standard cell library extension is crucial for maximizing Quality of Results (QoR) in modern VLSI design. We introduce CellE, a novel framework that leverages formal methods to achieve exhaustive discovery of functionally equivalent subcircuits. CellE applies equality saturation to the post-mapping netlist, generating an e-graph to cluster all functionally equivalent implementations. This canonical representation enables an efficient pattern mining algorithm to select the most area-optimal standard cells. Experimental results show a 15.41% average area reduction (up to 23.64% over prior work). Furthermore, characterization in a commercial flow demonstrates an 8.00% average delay reduction, confirming CellE's superior QoR optimization capabilities.

翻译：自动化标准单元库扩展对于最大化现代超大规模集成电路设计的结果质量至关重要。本文提出CellE，一种利用形式化方法实现功能等价子电路穷举发现的新型框架。CellE将等式饱和技术应用于映射后网表，通过生成e-图来聚类所有功能等价的电路实现。这种规范表示使得高效的模式挖掘算法能够选择面积最优的标准单元。实验结果显示平均面积减少15.41%（较现有工作最高提升23.64%）。在商用设计流程中的特性分析进一步表明平均延迟降低8.00%，验证了CellE卓越的结果质量优化能力。