Semiconductor intellectual property (IP) theft incurs estimated annual losses ranging from $225 billion to $600 billion. Despite initiatives like the CHIPS Act, many semiconductor designs remain vulnerable to reverse engineering (RE). IP Camouflage is a recent breakthrough that expands beyond the logic gate hiding of traditional camouflage through "mimetic deception," where an entire module masquerades as a different IP. However, it faces key limitations: requires a high-overhead post-generation rectification step, is not easily scalable, and uses an AIG logic representation that is mismatched with standard RE analysis flows. This paper addresses these shortcommings by introducing two novel, end-to-end models. We propose a Graph-Matching algorithm to solve the representation problem and a DNAS-based NAND Array model to achieve scalability. To facilitate this, we also introduce a mimicry-aware partitioning method, enabling a divide-and-conquer approach for large-scale designs. Our results demonstrate that these models are resilient to SAT and GNN-RE attacks, providing efficient and scalable paths for end-to-end deceptive IP design.

翻译：半导体知识产权（IP）盗窃造成的年度损失估计在2250亿至6000亿美元之间。尽管有《芯片法案》等举措，许多半导体设计仍易受逆向工程（RE）攻击。IP伪装是近期的一项突破性技术，它通过"模仿欺骗"——即整个模块伪装成不同的IP——超越了传统伪装技术的逻辑门隐藏范畴。然而，该技术存在关键局限性：需要高开销的后生成校正步骤、不易扩展，且使用的AIG逻辑表示与标准RE分析流程不匹配。本文通过引入两种新颖的端到端模型来解决这些缺陷。我们提出图匹配算法来解决表示问题，并采用基于DNAS的NAND阵列模型实现可扩展性。为此，我们还引入了模仿感知的分区方法，为大规模设计实现分治策略。实验结果表明，这些模型能有效抵抗SAT和GNN-RE攻击，为端到端欺骗性IP设计提供了高效且可扩展的路径。