Since polar codes were proposed, improving the performance of polar codes at limited code lengths has received significant attention. One of the effective solutions is a series of list flip decoders proposed in recent years. To further enhance performance, we proposed a parity-check-aided dynamic successive cancellation list flip (PC-DSCLF) decoder in this paper. First, we designed a simplified flip metric, and proved by simulations that this simplification hardly affects the error-correction performance of list flip decoders. Subsequently, we optimized the existing allocation scheme for parity check (PC) bits, and then designed the first multi-PC-aided scheme with the dynamic characteristic for list flip decoders. The dynamic characteristic refers to an excellent ability to correct higher-order errors, which is beneficial for error-correction performance improvement. Meantime, the multi-PC-aided scheme to list flip decoders brings more flexible distributed check bits, which can narrow down the range for searching error bits and achieve a more efficient early termination. Simulation results showed that without error-correction performance loss, PC-DSCLF decoder shows up to 51.1% average complexity gain with respect to the state-of-the-art list flip decoder at practical code lengths. Lower average complexity leads to lower average energy consumption and lower average decoding delay.

翻译：自极化码提出以来，在有限码长下提升其性能一直备受关注。近年来提出的一系列列表翻转译码器是有效的解决方案之一。为进一步增强性能，本文提出了一种奇偶校验辅助的动态逐次消除列表翻转（PC-DSCLF）译码器。首先，我们设计了一种简化翻转度量，并通过仿真证明该简化几乎不影响列表翻转译码器的纠错性能。随后，我们优化了现有的奇偶校验（PC）比特分配方案，并首次为列表翻转译码器设计了具有动态特征的多PC辅助方案。动态特征指代出色的高阶错误纠正能力，这有利于纠错性能的提升。同时，列表翻转译码器采用多PC辅助方案可带来更灵活的分布式校验比特，从而缩小错误比特的搜索范围并实现更高效的提前终止。仿真结果表明，在不损失纠错性能的前提下，PC-DSCLF译码器在实际码长下相比当前最先进的列表翻转译码器，平均复杂度增益高达51.1%。更低平均复杂度意味着更低平均能耗与更低平均译码延迟。