High-level synthesis (HLS) tools have provided significant productivity enhancements to the design flow of digital systems in recent years, resulting in highly-optimized circuits, in terms of area and latency. Given the evolution of hardware attacks, which can render them vulnerable, it is essential to consider security as a significant aspect of the HLS design flow. Yet the need to evaluate a huge number of functionally equivalent de-signs of the HLS design space challenges hardware security evaluation methods (e.g., fault injection - FI campaigns). In this work, we propose an evaluation methodology of hardware security properties of HLS-produced designs using state-of-the-art Graph Neural Network (GNN) approaches that achieves significant speedup and better scalability than typical evaluation methods (such as FI). We demonstrate the proposed methodology on a Double Modular Redundancy (DMR) coun-termeasure applied on an AES SBox implementation, en-hanced by diversifying the redundant modules through HLS directives. The experimental results show that GNNs can be efficiently trained to predict important hardware security met-rics concerning fault attacks (e.g., critical and detection error rates), by using regression. The proposed method predicts the fault vulnerability metrics of the HLS-based designs with high R-squared scores and achieves huge speedup compared to fault injection once the training of the GNN is completed.

翻译：近年来，高层综合（HLS）工具在数字系统设计流程中显著提升了生产力，生成了在面积和延迟方面高度优化的电路。鉴于硬件攻击的演变可能使电路变得脆弱，将安全性作为HLS设计流程的重要考量因素至关重要。然而，HLS设计空间中大量功能等效的设计需要评估，这对硬件安全评估方法（如故障注入-FI攻击）提出了挑战。本研究提出了一种利用最先进的图神经网络（GNN）方法评估HLS生成设计硬件安全属性的方法，该方法在典型评估方法（如FI）基础上实现了显著的加速和更好的可扩展性。我们通过应用于AES SBox实现的双模块冗余（DMR）对策演示了所提出的方法，并通过HLS指令多样化冗余模块增强了该对策。实验结果表明，GNN可以通过回归高效训练，预测与故障攻击相关的重要硬件安全指标（如关键错误率和检测错误率）。所提出的方法以高R-squared评分预测基于HLS设计的故障脆弱性指标，并且在GNN训练完成后，相比故障注入实现了巨大的加速。