Quantum computers have the potential to solve certain complex problems in a much more efficient way than classical computers. Nevertheless, current quantum computer implementations are limited by high physical error rates. This issue is addressed by Quantum Error Correction (QEC) codes, which use multiple physical qubits to form a logical qubit to achieve a lower logical error rate, with the surface code being one of the most commonly used. The most time-critical step in this process is interpreting the measurements of the physical qubits to determine which errors have most likely occurred - a task called decoding. Consequently, the main challenge for QEC is to achieve error correction with high accuracy within the tight $1μs$ decoding time budget imposed by superconducting qubits. State-of-the-art QEC approaches trade accuracy for latency. In this work, we propose an FPGA accelerator for a Neural Network based decoder as a way to achieve a lower logical error rate than current methods within the tight time constraint, for code distance up to d=7. We achieved this goal by applying different hardware-aware optimizations to a high-accuracy GNN-based decoder. In addition, we propose several accelerator optimizations leading to the FPGA-based decoder achieving a latency smaller than $1μs$, with a lower error rate compared to the state-of-the-art.

翻译：量子计算机在解决某些复杂问题方面具有比经典计算机更高效的潜力。然而，当前量子计算机的实现受限于高物理错误率。这一问题通过量子纠错码加以解决，该码利用多个物理量子比特构成一个逻辑量子比特，以实现更低的逻辑错误率，其中表面码是最常用的纠错码之一。在此过程中最为耗时的关键步骤是解释物理量子比特的测量结果，以确定最可能发生的错误——这一任务被称为解码。因此，量子纠错的主要挑战在于在超导量子比特所施加的严格$1μs$解码时间预算内，实现高精度的纠错。现有量子纠错方法在延迟与精度之间进行权衡。在本工作中，我们提出了一种基于神经网络的解码器的FPGA加速器，以在严格时间约束下实现比现有方法更低的逻辑错误率，适用于码距最高为$d=7$的情况。我们通过将多种硬件感知优化应用于高精度的基于图神经网络的解码器来实现这一目标。此外，我们提出了若干加速器优化方案，使得基于FPGA的解码器在实现低于$1μs$延迟的同时，相比现有技术具有更低的错误率。