Hardware generation languages (HGLs) increase hardware design productivity by creating parameterized modules and test benches. Unfortunately, existing tools are not widely adopted due to several demerits, including limited support for asynchronous circuits and unknown states, lack of concise and efficient language features, and low integration of simulation and verification functions. This paper introduces PyHGL, an open-source Python framework that aims to provide a simple and unified environment for hardware generation, simulation, and verification. PyHGL language is a syntactical superset of Python, which greatly reduces the lines of code (LOC) and improves productivity by providing unique features such as dynamic typing, vectorized operations, and automatic port deduction. In addition, PyHGL integrates an event-driven simulator that simulates the asynchronous behaviors of digital circuits using three-state logic. We also propose an algorithm that eliminates the calculation and transmission overhead of unknown state propagation for binary stimuli. The results suggest that PyHGL code is up to 6.1x denser than traditional RTL and generates high-quality synthesizable RTL code. Moreover, the optimized simulator achieves 2.9x speed up and matches the performance of a commonly used open-source logic simulator.

翻译：硬件生成语言（HGL）通过创建参数化模块和测试平台来提高硬件设计效率。然而，现有工具因存在诸多缺陷而未得到广泛应用，包括对异步电路和未知状态支持不足、缺乏简洁高效的语言特性，以及仿真与验证功能集成度低等。本文提出PyHGL——一个开源Python框架，旨在为硬件生成、仿真和验证提供简单统一的环境。PyHGL语言是Python的语法超集，通过提供动态类型、向量化运算和自动端口推导等独特特性，大幅减少代码行数并提升设计效率。此外，PyHGL集成了事件驱动仿真器，采用三态逻辑模拟数字电路的异步行为。我们还提出一种算法，消除了二进制激励下未知状态传播的计算与传输开销。实验结果表明，PyHGL代码密度较传统RTL提升达6.1倍，且能生成高质量综合可用的RTL代码。与此同时，优化后的仿真器取得2.9倍加速，性能与常用开源逻辑仿真器相当。