Debugging represents a time-consuming and labor-intensive task in hardware design, with bug localization constituting a substantial portion of this process. While spectrum-based bug localization techniques have achieved remarkable success in software domains and shown promise for hardware description languages, their effectiveness severely degrades in sequential designs. Unlike software programs, hardware designs exhibit intrinsic temporal characteristics that create fundamental challenges: timing misalignment between bug activation and observation, and progressive error propagation through state elements that obscures the root cause. To address these limitations, we propose Pecker, a novel bug localization framework that reconstructs the broken causal chain in sequential designs. Our approach introduces two key innovations: temporal backtracking using Estimated Minimal Propagation Cycles to identify potential activation cycles, strategic trace pruning to eliminate state pollution effects. We evaluate Pecker on comprehensive benchmarks comprising both combinational and sequential circuits. Experimental results demonstrate that Pecker effectively localizes 51%/80%/85% bugs within Top-1/3/5 ranks respectively, significantly outperforming state-of-the-art techniques. Notably, Pecker maintains robust performance across circuit complexities while existing methods exhibit severe degradation on sequential designs.

翻译：在硬件设计中，调试是一项耗时且劳动密集型的任务，而缺陷定位在其中占据了相当大的比重。尽管基于频谱的缺陷定位技术在软件领域取得了显著成功，并在硬件描述语言中展现出潜力，但其在时序设计中的有效性严重下降。与软件程序不同，硬件设计具有固有的时序特性，这带来了根本性挑战：缺陷激活与观测之间的时序失准，以及通过状态元件进行的渐进式错误传播掩盖了根本原因。为应对这些局限性，我们提出了Pecker，一种通过重构时序设计中被破坏的因果链来进行缺陷定位的新颖框架。我们的方法引入了两项关键创新：利用估计最小传播周期进行时序回溯以识别潜在的激活周期，以及通过策略性迹线剪枝来消除状态污染效应。我们在包含组合电路与时序电路的综合性基准测试集上评估了Pecker。实验结果表明，Pecker能分别在Top-1/3/5排名内有效定位51%/80%/85%的缺陷，显著优于现有最先进技术。值得注意的是，Pecker在不同电路复杂度下均保持稳健性能，而现有方法在时序设计上表现出严重的性能退化。