Neural networks with a latency requirement on the order of microseconds, like the ones used at the CERN Large Hadron Collider, are typically deployed on FPGAs fully unrolled and pipelined. A bottleneck for the deployment of such neural networks is area utilization, which is directly related to the required constant matrix-vector multiplication (CMVM) operations. In this work, we propose an efficient algorithm for implementing CMVM operations with distributed arithmetic on FPGAs that simultaneously optimizes for area consumption and latency. The algorithm achieves resource reduction similar to state-of-the-art algorithms while being significantly faster to compute. The proposed algorithm is open-sourced and integrated into the \texttt{hls4ml} library, a free and open-source library for running real-time neural network inference on FPGAs. We show that the proposed algorithm can reduce on-chip resources by up to a third for realistic, highly quantized neural networks while simultaneously reducing latency, enabling the implementation of previously infeasible networks.

翻译：微秒级延迟需求的神经网络（如CERN大型强子对撞机中使用的网络）通常部署在完全展开和流水线化的FPGA上。此类神经网络部署的瓶颈在于面积利用率，该指标直接与所需的常数矩阵-向量乘法（CMVM）操作相关。本文提出了一种基于分布式算术实现CMVM操作的高效算法，该算法在FPGA上同时优化面积消耗和延迟。该算法在实现资源缩减效果与现有最优算法相当的同时，显著提升了计算速度。所提算法已开源并集成至\texttt{hls4ml}库（一个用于在FPGA上实现实时神经网络推理的免费开源库）。结果表明，对于实际高度量化的神经网络，该算法可减少多达三分之一的芯片资源，同时降低延迟，从而使得先前不可行的网络得以实现。