As the demand for high-speed and low-power electronics continues to grow, the quasi-delay-insensitive (QDI) asynchronous domain of digital design has emerged as a promising alternative to traditional clock-based designs. However, the adoption of the paradigm has been greatly limited due to the lack of mature computer-aided design (CAD) tools and a substantially larger area footprint, owing to various architectural constraints. Monolithic-3D (M3D) technology has recently paved the way for manufacturing highly dense integrated circuits (ICs) through sequential integration, resulting in a reduced area footprint, shorter wirelengths, and increased performance. In this study, we integrate M3D technology with QDI Null Convention Logic (NCL) and propose a design methodology for the implementation of M3D-based NCL standard cells, aimed at mitigating the area inefficiencies of traditional planar or 2D counterparts. Furthermore, we employed the threshold gates to design an M3D-NCL unsigned array multiplier circuit. Simulation results suggest that, for a conservative wirelength reduction resulting from M3D implementation, a substantial area reduction of 44% can be achieved while simultaneously reducing delay and power by approximately 31% and 17%, respectively.

翻译：随着高速低功耗电子器件需求持续增长，数字设计中准延迟不敏感异步域已成为传统时钟基设计方案的重要替代路径。然而，受限于缺乏成熟的计算机辅助设计工具以及架构约束导致的显著面积开销，该设计范式的应用推广始终面临较大制约。单片三维集成技术通过顺序集成工艺，为制造高密度集成电路开辟了新路径，可实现面积缩减、互连线长度缩短及性能提升。本研究将单片三维集成技术与准延迟不敏感空值约定逻辑相融合，提出面向单片三维集成空值约定逻辑标准单元的设计方法论，旨在缓解传统平面或二维标准单元的面积效率缺陷。进一步地，我们采用阈值门电路设计了基于M3D-NCL的无符号阵列乘法器电路。仿真结果表明，在单片三维集成保守估算的互连线长度缩减条件下，该方案可实现44%的面积缩减，同时分别降低约31%的延迟和17%的功耗。