The current over-provisioned heterogeneous multi-cores require effective run-time optimization strategies, and the run-time power monitoring subsystem is paramount for their success. Several state-of-the-art methodologies address the design of a run-time power monitoring infrastructure for generic computing platforms. However, the power model's training requires time-consuming gate-level simulations that, coupled with the ever-increasing complexity of the modern heterogeneous platforms, dramatically hinder the usability of such solutions. This paper introduces Blink, a scalable framework for the fast and automated design of run-time power monitoring infrastructures targeting computing platforms implemented on FPGA. Blink optimizes the time-to-solution to deliver the run-time power monitoring infrastructure by replacing traditional methodologies' gate-level simulations and power trace computations with behavioral simulations and direct power trace measurements. Applying Blink to multiple designs mixing a set of HLS-generated accelerators from a state-of-the-art benchmark suite demonstrates an average time-to-solution speedup of 18 times without affecting the quality of the run-time power estimates.

翻译：当前过度配置的异构多核系统需要有效的运行时优化策略，而运行时功耗监测子系统对此至关重要。现有多种先进方法致力于为通用计算平台设计运行时功耗监测基础设施。然而，功耗模型的训练需要耗时的门级仿真，加之现代异构平台日益增长的复杂性，严重阻碍了此类解决方案的实用性。本文提出Blink——一个面向FPGA实现的计算平台、用于快速自动化设计运行时功耗监测基础设施的可扩展框架。Blink通过用行为仿真和直接功耗轨迹测量替代传统方法的门级仿真与功耗轨迹计算，优化了交付运行时功耗监测基础设施的求解时间。将Blink应用于混合多种来自先进基准测试套件的高层次综合生成加速器的多个设计实例，在保证运行时功耗估计质量不变的前提下，平均求解时间加速比达到18倍。