Register Transfer Level (RTL) design translates high-level specifications into hardware using HDLs such as Verilog. Although LLM-based RTL generation is promising, the scarcity of functionally verifiable high-quality data limits both accuracy and diversity. Existing post-training typically produces a single HDL implementation per specification, lacking awareness of RTL variations needed for different design goals. We propose RTLSeek, a post-training paradigm that applies rule-based Diversity-Oriented Reinforcement Learning to improve RTL correctness and diversity. Our Diversity-Centric Multi-Objective Reward Scheduling integrates expert knowledge with EDA feedback, and a three-stage framework maximizes the utility of limited data. Experiments on the RTLLM benchmark show that RTLSeek surpasses prior methods, with ablation results confirming that encouraging broader design-space exploration improves RTL quality and achieves the principle of "the more generated, the better results." Implementation framework, including the dataset, source code, and model weights, is shown at https://anonymous.4open.science/r/DAC2026ID71-ACB4/.

翻译：寄存器传输级设计通过Verilog等硬件描述语言将高层次规约转换为硬件实现。尽管基于LLM的RTL生成前景广阔，但功能可验证的高质量数据稀缺限制了生成结果的准确性与多样性。现有后训练方法通常为每个规约生成单一HDL实现，缺乏针对不同设计目标所需的RTL变体感知能力。我们提出RTLSeek后训练范式，采用基于规则的多样性导向强化学习提升RTL正确性与多样性。其中，多样性中心多目标奖励调度机制整合专家知识与EDA反馈，三阶段框架则最大化有限数据的效用。在RTLLM基准上的实验表明，RTLSeek超越先前方法，消融实验证实鼓励更广泛设计空间探索可提升RTL质量，实现"生成越多，结果越优"的原则。实现框架（含数据集、源代码及模型权重）见https://anonymous.4open.science/r/DAC2026ID71-ACB4/。