The growing complexity of cyber-physical systems (CPSs) calls for early prototyping tools that combine accuracy, speed, and usability. Virtual Platforms (VPs) provide fast functional simulation, but hybrid co-emulation solutions, in which key digital components are deployed on FPGA, become necessary when accurate timing modelling is required and RTL simulation is too costly. However, existing hybrid emulation tools are mostly proprietary, and rely on vendor-specific FPGA features. To address this gap, we introduce an open-source framework that connects SystemC-based VPs with FPGA emulation, enabling full-system co-emulation of digital and non-digital components. The FPGA accelerates the execution of main digital subsystems, while a wrapper coordinates timing and communication with the VP through JTAG, maintaining synchronization with simulated peripherals. Evaluations using a RISC-V SoC, with an example in the biosignals processing domain, show up to 2500x speedup compared to RTL simulation, while maintaining less than 2x total simulation time relative to pure FPGA emulation.

翻译：信息物理系统（CPSs）日益增长的复杂性要求开发兼具精度、速度和易用性的早期原型验证工具。虚拟平台（VPs）能提供快速功能仿真，但当需要精确时序建模且RTL仿真代价过高时，必须采用将关键数字组件部署于FPGA的混合协同仿真方案。然而现有混合仿真工具多为商业专有方案，且依赖厂商特定FPGA特性。为填补这一空白，我们提出开源框架，实现基于SystemC的VP与FPGA仿真的互联，支持数字及非数字组件的全系统协同仿真。FPGA加速主数字子系统的执行，而协调模块通过JTAG接口管理VP的时序与通信，维持与仿真外设的同步。基于RISC-V SoC（以生物信号处理领域为例）的评估显示，相较于RTL仿真可实现最高2500倍加速，同时总仿真时间相比纯FPGA仿真仅增加不到2倍。