While FPGA is a suitable platform for implementing cryptographic algorithms, there are several challenges associated with implementing Optimal Ate pairing on FPGA, such as security, limited computing resources, and high power consumption. To overcome these issues, this study introduces three approaches that can execute the optimal Ate pairing on Barreto-Naehrig curves using Jacobean coordinates with the goal of reaching 128-bit security on the Genesys board. The first approach is a pure software implementation utilizing the MicroBlaze processor. The second involves a combination of software and hardware, with key operations in $F_{p}$ and $F_{p^{2}}$ being transformed into IP cores for the MicroBlaze. The third approach builds on the second by incorporating parallelism to improve the pairing process. The utilization of multiple MicroBlaze processors within a single system offers both versatility and parallelism to speed up pairing calculations. A variety of methods and parameters are used to optimize the pairing computation, including Montgomery modular multiplication, the Karatsuba method, Jacobean coordinates, the Complex squaring method, sparse multiplication, squaring in $G_{\phi 6}F_{p^{12}}$, and the addition chain method. The proposed systems are designed to efficiently utilize limited resources in restricted environments, while still completing tasks in a timely manner.

翻译：尽管FPGA是实现密码算法的合适平台，但在其上实现最优Ate对偶仍面临安全性、有限计算资源及高功耗等多重挑战。为克服这些问题，本研究提出三种可在Genesys开发板上采用雅可比坐标在Barreto-Naehrig曲线上执行最优Ate对偶的方法，目标达到128位安全等级。第一种方法基于MicroBlaze处理器的纯软件实现；第二种采用软硬件协同方案，将$F_{p}$和$F_{p^{2}}$域的关键运算转化为MicroBlaze的IP核；第三种方法在第二种基础上引入并行机制以提升对偶效率。通过在同一系统中部署多个MicroBlaze处理器，既保证了灵活性又通过并行化加速了对偶计算。研究采用多种方法与参数优化对偶运算，包括Montgomery模乘、Karatsuba方法、雅可比坐标、复数平方方法、稀疏乘法、$G_{\phi 6}F_{p^{12}}$域平方运算及加法链方法。所提系统旨在受限环境中高效利用有限资源，同时确保任务及时完成。