The growing complexity of hardware design and the widening gap between high-level specifications and register-transfer level (RTL) implementation hinder rapid prototyping and system design. We introduce NL2GDS (Natural Language to Layout), a novel framework that leverages large language models (LLMs) to translate natural language hardware descriptions into synthesizable RTL and complete GDSII layouts via the open-source OpenLane ASIC flow. NL2GDS employs a modular pipeline that captures informal design intent, generates HDL using multiple LLM engines and verifies them, and orchestrates automated synthesis and layout. Evaluations on ISCAS'85 and ISCAS'89 benchmark designs demonstrate up to 36% area reduction, 35% delay reduction, and 70% power savings compared to baseline designs, highlighting its potential to democratize ASIC design and accelerate hardware innovation.

翻译：硬件设计日益增长的复杂性，以及高层次规范与寄存器传输级实现之间不断扩大的鸿沟，阻碍了快速原型设计与系统开发。我们提出了NL2GDS（自然语言到版图），这是一个新颖的框架，它利用大语言模型将自然语言硬件描述转换为可综合的RTL，并通过开源的OpenLane ASIC流程生成完整的GDSII版图。NL2GDS采用模块化流程，能够捕捉非正式的设计意图，使用多个LLM引擎生成并验证硬件描述语言，并协调自动化的综合与版图生成。在ISCAS'85和ISCAS'89基准设计上的评估表明，与基线设计相比，该框架可实现高达36%的面积缩减、35%的延迟降低以及70%的功耗节省，突显了其在普及ASIC设计和加速硬件创新方面的潜力。