Recent advances in LLMs have sparked growing interest in applying them to hardware design automation, particularly for accurate RTL code generation. Prior efforts follow two largely independent paths: (i) training domain-adapted RTL models to internalize hardware semantics, (ii) developing agentic systems that leverage frontier generic LLMs guided by simulation feedback. However, these two paths exhibit complementary strengths and weaknesses. In this work, we present ACE-RTL that unifies both directions through Agentic Context Evolution (ACE). ACE-RTL integrates an RTL-specialized LLM, trained on a large-scale dataset of 1.7 million RTL samples, with a frontier reasoning LLM through three synergistic components: the generator, reflector, and coordinator. These components iteratively refine RTL code toward functional correctness. We further analyze a parallel scaling strategy that reduces wall-clock iterations to first success by exploring diverse debugging trajectories concurrently. On the CVDP benchmark, ACE-RTL achieves up to a 41.02% pass rate improvement over 14 competitive baselines.

翻译：近期大语言模型的进展激发了业界对其应用于硬件设计自动化的浓厚兴趣，尤其聚焦于精确的RTL代码生成。现有研究遵循两条相对独立的路径：(i) 训练领域适配的RTL模型以内化硬件语义，(ii) 开发基于仿真反馈引导前沿通用大语言模型的智能体系统。然而，这两种路径呈现出互补的优劣势。本文提出ACE-RTL，通过智能体上下文演化将两个方向统一起来。ACE-RTL集成了一个在170万RTL样本大规模数据集上训练的专用大语言模型，并通过生成器、反射器和协调器三个协同组件与前沿推理大语言模型协同工作。这些组件通过迭代方式逐步优化RTL代码直至功能正确。我们进一步分析了一种并行扩展策略，通过同时探索多样化的调试轨迹，减少达到首次成功所需的实际迭代次数。在CVDP基准测试上，ACE-RTL相较于14个具有竞争力的基线模型，通过率提升了高达41.02%。