Generating synthesizable Verilog for large, hierarchical hardware designs remains a significant challenge for large language models (LLMs), which struggle to replicate the structured reasoning that human experts employ when translating complex specifications into RTL. When tasked with producing hierarchical Verilog, LLMs frequently lose context across modules, hallucinate interfaces, fabricate inter-module wiring, and fail to maintain structural coherence - failures that intensify as design complexity grows and specifications involve informal prose, figures, and tables that resist direct operationalization. To address these challenges, we present VeriGraphi, a framework that introduces a spec-anchored Knowledge Graph as the architectural substrate driving the RTL generation pipeline. VeriGraphi constructs a HDA, a structured knowledge graph that explicitly encodes module hierarchy, port-level interfaces, wiring semantics, and inter-module dependencies as first-class graph entities and relations. Built through iterative multi-agent analysis of the specification, this Knowledge Graph provides a deterministic, machine-checkable structural scaffold before code generation. Guided by the KG, a progressive coding module incrementally generates pseudo-code and synthesizable RTL while enforcing interface consistency and dependency correctness at each submodule stage. We evaluate VeriGraphi on a benchmark of three representative specification documents from the National Institute of Standards and Technology and their corresponding implementations, and we present a RV32I processor as a detailed case study to illustrate the full pipeline. The results demonstrate that VeriGraphi enables reliable hierarchical RTL generation with minimal human intervention for RISC-V, marking a significant milestone for LLM-generated hardware design while maintaining strong functional correctness.

翻译：为大规模分层硬件设计生成可综合Verilog代码，对大型语言模型（LLM）仍是一项重大挑战——LLM难以复现人类专家在将复杂规范转化为寄存器传输级（RTL）设计时采用的推理性结构化思维。当LLM被要求生成分层Verilog时，常出现跨模块上下文丢失、接口幻觉化、模块间连线虚构以及结构一致性缺失等问题——这些缺陷随设计复杂度增长而加剧，尤其当规范涉及难以直接形式化的非正式文本、图表和表格时。为应对这些挑战，我们提出VeriGraphi框架，该框架引入基于规范的锚定知识图谱作为驱动RTL生成流水线的架构基板。VeriGraphi构建了一种结构化知识图谱（HDA），将模块层级、端口级接口、连线语义及模块间依赖关系显式编码为一阶图实体与关系。该知识图谱通过对规范文档进行迭代式多智能体分析而生成，在代码生成前提供确定性、可机器校验的结构框架。在知识图谱引导下，渐进式编码模块逐步生成伪代码与可综合RTL，并在每个子模块阶段强制确保接口一致性及依赖正确性。我们基于国家标准与技术研究院的三份代表性规范文档及其对应实现构成的基准测试集对VeriGraphi进行评估，并以RV32I处理器为例进行完整流水线案例分析。结果表明，VeriGraphi能够以最少人工干预实现RISC-V的可靠分层RTL生成，在保持强功能正确性的同时，标志着LLM生成硬件设计领域的重要里程碑。