Debugging represents a time-consuming and labor-intensive task in hardware design, with bug localization constituting a substantial portion of this process. While spectrum-based bug localization techniques have achieved remarkable success in software domains and shown promise for hardware description languages, their effectiveness severely degrades in sequential designs. Unlike software programs, hardware designs exhibit intrinsic temporal characteristics that create fundamental challenges: timing misalignment between bug activation and observation, and progressive error propagation through state elements that obscures the root cause. To address these limitations, we propose Pecker, a novel bug localization framework that reconstructs the broken causal chain in sequential designs. Our approach introduces two key innovations: temporal backtracking using Estimated Minimal Propagation Cycles to identify potential activation cycles, strategic trace pruning to eliminate state pollution effects. We evaluate Pecker on comprehensive benchmarks comprising both combinational and sequential circuits. Experimental results demonstrate that Pecker effectively localizes 51%/80%/85% bugs within Top-1/3/5 ranks respectively, significantly outperforming state-of-the-art techniques. Notably, Pecker maintains robust performance across circuit complexities while existing methods exhibit severe degradation on sequential designs.

翻译：调试是硬件设计中一项耗时费力的任务，而缺陷定位占据了该流程的绝大部分。尽管基于频谱的缺陷定位技术在软件领域取得了显著成功，并在硬件描述语言中展现出潜力，但其在时序设计中的有效性严重下降。与软件程序不同，硬件设计具有内在的时间特性，这带来了根本性的挑战：缺陷激活与观测之间的时序错位，以及通过状态元件逐步传播的错误扩散，掩盖了根本原因。为解决这些局限性，我们提出Pecker，一种新颖的缺陷定位框架，通过重构时序设计中断裂的因果链来定位缺陷。我们的方法引入两项关键创新：利用估计最小传播周期进行时间回溯以识别潜在激活周期，以及策略性迹修剪以消除状态污染效应。我们在包含组合电路和时序电路的综合基准测试上评估了Pecker。实验结果表明，Pecker在Top-1/3/5排名内分别有效定位了51%/80%/85%的缺陷，显著优于现有最先进技术。值得注意的是，Pecker在不同电路复杂度下均保持稳健性能，而现有方法在时序设计上则表现出严重退化。