Chiplet architectures are on the rise as they promise to overcome the scaling challenges of monolithic chips. A key component of such architectures is an efficient inter-chiplet interconnect (ICI). The ICI design space is huge as there are many degrees of freedom such as the number, size, and placement of chiplets, the topology and bandwidth of links, the packaging technology, and many more. While ICI simulators are important to get reliable performance estimates, they are not fast enough to explore hundreds of thousands of design points or to be used as a cost function for optimization algorithms or machine learning models. To address this issue, we present RapidChiplet, a fast and easy to use ICI latency and throughput prediction toolchain. Compared to cycle-level simulations, we trade 0.25%-30.15% of accuracy for 427x-137,682x speedup.

翻译：小芯片架构因其有望克服单芯片的扩展性挑战而日益兴起。此类架构的一个关键组成部分是高效的小芯片间互连。由于存在诸多自由度，如小芯片的数量、尺寸与布局、链路的拓扑与带宽、封装技术等，小芯片间互连的设计空间极为庞大。虽然小芯片间互连仿真器对于获得可靠的性能评估至关重要，但其速度不足以探索数十万个设计点，也无法用作优化算法或机器学习模型的成本函数。为解决此问题，我们提出了RapidChiplet——一个快速易用的小芯片间互连延迟与吞吐量预测工具链。与周期级仿真相比，我们以牺牲0.25%-30.15%的精度为代价，换取了427倍至137,682倍的加速比。