Designing the power delivery network (PDN) in very large-scale integrated (VLSI) circuits is increasingly important, especially for nowadays low-power integrated circuit (IC) design. In order to ensure that the designed PDN enables a low level of voltage drop and noise which is required for the success of IC design, accurate analysis of PDN is largely demanded and brings a challenge of computation during the whole process of IC design. This promotes the research of efficient and scalable simulation methods for PDN. However, the lack of sufficient public PDN benchmarks hinders the relevant research. % on this aspect since it is hard to conduct a rapid and clear comparison between different approaches to solving this problem. To this end, we construct and release a set of PDN benchmarks (named \emph{SRAM-PG}) from SRAM circuit design in this work. The benchmarks are obtained from realistic and state-of-the-art SRAM designs, following a workflow for generating the post-layout PDN netlists with full RC parasitics. With careful modeling of load currents, the benchmarks reflect the dynamic work mode of the IC and can be used for both transient and DC analysis. The benchmarks are derived from the designs for diverse applications. And, sharing them in the public domain with detailed descriptions would largely benefit the relevant research. The whole set of benchmarks is available at \href{github}{https://github.com/ShenShan123/SRAM-PG}.

翻译：在超大规模集成电路（VLSI）中设计电源分配网络（PDN）日益重要，尤其是对于当今低功耗集成电路（IC）设计而言。为确保所设计的PDN能够实现低电压降和低噪声这一IC设计成功的关键要求，对PDN进行精确分析的需求极为迫切，这也给IC设计的全过程带来了计算挑战。这推动了PDN高效可扩展仿真方法的研究。然而，缺乏充足的公开PDN基准测试阻碍了相关研究。为此，本研究从SRAM电路设计中构建并发布了一组PDN基准测试（命名为SRAM-PG）。这些基准测试来源于真实且先进的SRAM设计，遵循生成包含完整RC寄生参数的后版图PDN网表的工作流程。通过精细的负载电流建模，该基准测试反映了IC的动态工作模式，可用于瞬态和直流分析。这些基准测试源自面向多种应用的设计。将其公开共享并提供详细描述将极大促进相关研究。全部基准测试可在https://github.com/ShenShan123/SRAM-PG获取。