And-Inverter Graph (AIG)-based logic synthesis has been a cornerstone of digital design automation for several decades. While numerous optimization techniques have been developed for both technology-independent and technology-dependent synthesis stages, existing technology mapping approaches predominantly employ graph-covering strategies directly on AIG representations without adequately addressing complemented edge distribution. Neglecting inverters creates a significant disconnect: complemented edges are systematically overlooked in technology-independent cost functions, yet they abruptly become critical during technology-dependent mapping. In this work, we introduce a delay-driven pre-processing stage that operates prior to technology mapping, designed to strategically redistribute complemented edges and mitigate the inverter-induced costs on critical paths. Experimental validation demonstrates that our delay-targeted methodology not only preserves original delay characteristics but also enables performance improvements. Notably, arithmetic logic in the EPFL combinational benchmark exhibits particular sensitivity to this approach, with our method achieving an average delay reduction of 0.49% and a maximum improvement of 3.86% on the case sqrt.

翻译：基于与-逆变器图（AIG）的逻辑综合数十年来一直是数字设计自动化的基石。尽管在工艺无关和工艺相关综合阶段已发展出众多优化技术，现有技术映射方法主要直接在AIG表示上采用图覆盖策略，未能充分处理补边分布问题。忽视逆变器造成了显著脱节：补边在工艺无关代价函数中被系统性地忽略，却在工艺相关映射阶段突然成为关键。本文提出一种延迟驱动的预处理阶段，在技术映射之前执行，旨在策略性地重新分布补边，缓解关键路径上由逆变器引起的代价。实验验证表明，我们的延迟导向方法不仅保持原始延迟特性，还能实现性能提升。值得注意的是，EPFL组合基准测试中的算术逻辑对该方法尤为敏感，在sqrt案例上实现了平均0.49%的延迟降低，最大改进达3.86%。