FPGA programming is more complex as compared to Central Processing Units (CPUs) and Graphics Processing Units (GPUs). The coding languages to define the abstraction of Register Transfer Level (RTL) in High Level Synthesis (HLS) for FPGA platforms have emerged due to the laborious complexity of Hardware Description Languages (HDL). The HDL and High Level Synthesis (HLS) became complex when FPGA is adopted in high-performance parallel programs in multicore platforms of data centers. Writing an efficient host-side parallel program to control the hardware kernels placed in stacks of FPGAs is challenging and strenuous. The unavailability of efficient high level parallel programming tools for multi core architectures makes multicore parallel programming very unpopular for the masses. This work proposes an extension of FastFlow where data flows in hardware kernels can be executed efficiently in FPGA stacks. Here host side codes are generated automatically from simple csv files. The programmer needs to specify four simple parameters in these csv file: FPGA IDs, source, destination nodes, hardware kernel names. The proposed tool flow uses FastFlow libraries with Vitis to develop efficient and scalable parallel programs for FPGA stacks in data centers. The evidence from the implementation shows that the integration of FastFlow with Vitis reduces 96 % coding effort (in terms of number of lines) as compared to existing Vitis solutions.

翻译：与中央处理器（CPU）和图形处理器（GPU）相比，现场可编程门阵列（FPGA）的编程更为复杂。由于硬件描述语言（HDL）的复杂性较高，为FPGA平台定义高层次综合（HLS）中寄存器传输级（RTL）抽象的描述语言应运而生。当FPGA应用于数据中心多核平台的高性能并行程序时，HDL和高层次综合（HLS）变得尤为复杂。编写高效的主机端并行程序以控制部署在FPGA堆栈中的硬件内核，是一项具有挑战性且费力的任务。由于缺乏针对多核架构的高效高级并行编程工具，多核并行编程在大众中并不普及。本研究提出了一种FastFlow的扩展方案，使得硬件内核中的数据流能够在FPGA堆栈中高效执行。在此方案中，主机端代码可从简单的CSV文件自动生成。程序员仅需在这些CSV文件中指定四个简单参数：FPGA ID、源节点、目标节点以及硬件内核名称。所提出的工具流结合FastFlow库与Vitis，可为数据中心FPGA堆栈开发高效且可扩展的并行程序。实验结果表明，与现有Vitis解决方案相比，FastFlow与Vitis的集成可减少96%的编码工作量（以代码行数计）。