This paper presents the implementation and evaluation of the H (hypervisor) extension for the RISC-V instruction set architecture (ISA) on top of the gem5 microarchitectural simulator. The RISC-V ISA, known for its simplicity and modularity, has seen widespread adoption in various computing domains. The H extension aims to enhance RISC-V's capabilities for cloud computing and virtualization. In this paper, we present the architectural integration of the H extension into gem5, an open-source, modular platform for computer system architecture research. We detail the modifications required in gem5's CPU models and virtualization support to accommodate the H extension. We also present evaluation results regarding the performance impact and functional correctness of the extension's implementation on gem5. This study not only provides a pathway for further research and development of RISC-V extensions but also contributes valuable insights into the optimization of the gem5 simulator for advanced architectural features.

翻译：本文介绍了在gem5微架构模拟器上实现和评估RISC-V指令集架构（ISA）的H（管理程序）扩展。RISC-V ISA以其简洁性和模块化特性著称，已在多个计算领域得到广泛应用。H扩展旨在增强RISC-V在云计算和虚拟化方面的能力。本文阐述了将H扩展架构集成到gem5（一个用于计算机系统架构研究的开源模块化平台）的过程。我们详细说明了为适配H扩展而对gem5的CPU模型和虚拟化支持进行的修改，并展示了该扩展在gem5上实现的性能影响和功能正确性的评估结果。本研究不仅为RISC-V扩展的进一步研发提供了路径，还为优化gem5模拟器以支持先进架构特性提供了有价值的见解。