Register-Transfer Level (RTL) synthesis and summarization are central to hardware design automation but remain challenging for Large Language Models (LLMs) due to rigid HDL syntax, limited supervision, and weak alignment with natural language. Existing prompting and retrieval-augmented generation (RAG) methods have not incorporated symbolic planning, limiting their structural precision. We introduce SYMDIREC, a neuro-symbolic framework that decomposes RTL tasks into symbolic subgoals, retrieves relevant code via a fine-tuned retriever, and assembles verified outputs through LLM reasoning. Supporting both Verilog and VHDL without LLM fine-tuning, SYMDIREC achieves ~20% higher Pass@1 rates for synthesis and 15-20% ROUGE-L improvements for summarization over prompting and RAG baselines, demonstrating the benefits of symbolic guidance in RTL tasks.

翻译：寄存器传输级（RTL）综合与摘要是硬件设计自动化的核心，但由于严格的硬件描述语言（HDL）语法、有限的监督数据以及与自然语言的弱对齐性，对于大语言模型（LLMs）而言仍然具有挑战性。现有的提示工程和检索增强生成（RAG）方法未能融入符号规划，限制了其结构精确性。我们提出了SYMDIREC，一种神经符号框架，它将RTL任务分解为符号子目标，通过微调的检索器获取相关代码，并利用LLM推理组装经过验证的输出。SYMDIREC支持Verilog和VHDL，且无需对LLM进行微调，在综合任务上实现了比提示工程和RAG基线高出约20%的Pass@1成功率，在摘要任务上实现了15-20%的ROUGE-L提升，这证明了符号引导在RTL任务中的优势。