Generating synthesizable Verilog for large, hierarchical hardware designs remains a significant challenge for large language models (LLMs), which struggle to replicate the structured reasoning that human experts employ when translating complex specifications into RTL. When tasked with producing hierarchical Verilog, LLMs frequently lose context across modules, hallucinate interfaces, fabricate inter-module wiring, and fail to maintain structural coherence - failures that intensify as design complexity grows and specifications involve informal prose, figures, and tables that resist direct operationalization. To address these challenges, we present VeriGraphi, a framework that introduces a spec-anchored Knowledge Graph as the architectural substrate driving the RTL generation pipeline. VeriGraphi constructs a HDA, a structured knowledge graph that explicitly encodes module hierarchy, port-level interfaces, wiring semantics, and inter-module dependencies as first-class graph entities and relations. Built through iterative multi-agent analysis of the specification, this Knowledge Graph provides a deterministic, machine-checkable structural scaffold before code generation. Guided by the KG, a progressive coding module incrementally generates pseudo-code and synthesizable RTL while enforcing interface consistency and dependency correctness at each submodule stage. We evaluate VeriGraphi on a benchmark of three representative specification documents from the National Institute of Standards and Technology and their corresponding implementations, and we present a RV32I processor as a detailed case study to illustrate the full pipeline. The results demonstrate that VeriGraphi enables reliable hierarchical RTL generation with minimal human intervention for RISC-V, marking a significant milestone for LLM-generated hardware design while maintaining strong functional correctness.

翻译：为大型分层硬件设计生成可综合的Verilog代码，对大型语言模型（LLM）而言仍是一项重大挑战——这些模型难以复现人类专家在将复杂规格说明转化为RTL时所采用的结构化推理能力。在生成分层Verilog时，LLM常出现跨模块上下文丢失、接口幻觉、模块间连线虚构及结构一致性失效等问题，且这些缺陷会随设计复杂性增长及规格说明涉及非正式文本、图表和表格等难以直接操作化的内容而加剧。为应对这些挑战，我们提出VeriGraphi框架，该框架引入以规格说明锚定的知识图谱作为驱动RTL生成流水线的架构基板。VeriGraphi构建HDA这一结构化知识图谱，将模块层次结构、端口级接口、连线语义及模块间依赖关系显式编码为一阶图实体与关系。该知识图谱通过规格说明的迭代式多智能体分析构建，在代码生成前提供确定性的机器可验证结构骨架。在知识图谱引导下，渐进式编码模块逐步生成伪代码和可综合RTL，并在各子模块阶段强制执行接口一致性与依赖正确性。我们在国家标准化技术研究院三份代表性规格文档及其对应实现构成的基准测试上评估VeriGraphi，并以RV32I处理器作为详细案例研究展示完整流水线。结果表明，VeriGraphi能以极少人工干预实现RISC-V的可靠分层RTL生成，标志着LLM生成硬件设计在保持强功能正确性方面的重要里程碑。