Logic synthesis plays a crucial role in the digital design flow. It has a decisive influence on the final Quality of Results (QoR) of the circuit implementations. However, existing multi-level logic optimization algorithms often employ greedy approaches with a series of local optimization steps. Each step breaks the circuit into small pieces (e.g., k-feasible cuts) and applies incremental changes to individual pieces separately. These local optimization steps could limit the exploration space and may miss opportunities for significant improvements. To address the limitation, this paper proposes using e-graph in logic synthesis. The new workflow, named Esyn, makes use of the well-established e-graph infrastructure to efficiently perform logic rewriting. It explores a diverse set of equivalent Boolean representations while allowing technology-aware cost functions to better support delay-oriented and area-oriented logic synthesis. Experiments over a wide range of benchmark designs show our proposed logic optimization approach reaches a wider design space compared to the commonly used AIG-based logic synthesis flow. It achieves on average 15.29% delay saving in delay-oriented synthesis and 6.42% area saving for area-oriented synthesis.

翻译：摘要：逻辑综合在数字设计流程中起着至关重要的作用，并对电路实现的最终结果质量（QoR）具有决定性影响。然而，现有的多级逻辑优化算法通常采用贪心策略，通过一系列局部优化步骤实现。每一步将电路分解为小片段（例如k-可行割），并分别对每个片段进行增量式修改。这种局部优化步骤可能限制探索空间，并可能错失重大改进的机遇。为解决这一局限，本文提出在逻辑综合中引入e-graph。名为Esyn的新工作流利用成熟的e-graph基础设施高效执行逻辑重写，在探索多样化等价布尔表示的同时，引入工艺感知代价函数以更好支持面向延迟与面向面积的逻辑综合。对大量基准设计的实验表明，相较于常用的基于AIG的逻辑综合流程，所提出的逻辑优化方法能够覆盖更广泛的设计空间。在面向延迟的综合中平均节省15.29%的延迟，在面向面积的综合中平均节省6.42%的面积。