SRAM bitcells in retention mode behave as autonomous stochastic nonlinear dynamical systems. From observation of variability-aware transient noise simulations, we provide an unidimensional model, fully characterizable by conventional deterministic SPICE simulations, insightfully explaining the mechanism of intrinsic noise-induced bit flips. The proposed model is exploited to, first, explain the reported inaccuracy of existing closed-form near-equilibrium formulas aimed at predicting the mean time to failure and, secondly, to propose a closer estimate attractive in terms of CPU time.

翻译：保留模式下的SRAM存储单元表现为自主随机非线性动力学系统。通过对考虑变异性的瞬态噪声仿真观测，我们提出了一种完全可通过传统确定性SPICE仿真表征的一维模型，该模型能深入解释本征噪声诱发位翻转的机理。利用所提出的模型，首先解释了现有旨在预测平均失效时间的封闭形式近平衡公式存在的不准确性，其次提出了一种在CPU时间方面更具吸引力的更优估计方法。