Estimating the quality of register transfer level (RTL) designs is crucial in the electronic design automation (EDA) workflow, as it enables instant feedback on key performance metrics like area and delay without the need for time-consuming logic synthesis. While recent approaches have leveraged large language models (LLMs) to derive embeddings from RTL code and achieved promising results, they overlook the structural semantics essential for accurate quality estimation. In contrast, the control data flow graph (CDFG) view exposes the design's structural characteristics more explicitly, offering richer cues for representation learning. In this work, we introduce StructRTL, a novel structure-aware graph self-supervised learning framework for improved RTL design quality estimation. By learning structure-informed representations from CDFGs, StructRTL significantly outperforms prior art on various quality estimation tasks. To further boost performance, we incorporate a knowledge distillation strategy that transfers low-level insights from post-mapping netlists into the CDFG-based predictor. Experimental results demonstrate that StructRTL establishes new state-of-the-art results, highlighting the effectiveness of combining structural learning with cross-stage supervision.

翻译：评估寄存器传输级（RTL）设计的质量在电子设计自动化（EDA）工作流中至关重要，因为它能够无需耗时逻辑综合即可即时反馈关键性能指标（如面积和延迟）。尽管近期方法利用大型语言模型（LLMs）从RTL代码中提取嵌入并取得了有前途的结果，但它们忽略了对于准确质量估计至关重要的结构语义。相比之下，控制数据流图（CDFG）视图更明确地揭示了设计的结构特征，为表示学习提供了更丰富的线索。在本工作中，我们提出StructRTL，一种新型结构感知图自监督学习框架，用于改进RTL设计质量估计。通过从CDFG中学习结构信息表示，StructRTL在各种质量估计任务上显著优于先前技术。为进一步提升性能，我们引入一种知识蒸馏策略，将映射后网表的低级见解迁移至基于CDFG的预测器。实验结果表明，StructRTL建立了新的最优结果，突出了将结构学习与跨阶段监督相结合的有效性。