The development of a standard cell library involves characterization of a number of gate-level circuits at various cell-level abstractions. Verifying the behavior of these cells largely depends on the manual skills of the circuit designers. Especially challenging are the power management and data retention cells which must be checked thoroughly for voltage and power configurations in addition to their logic functionality. Also, when standard cells are extracted into various models, any inconsistencies in these models typically goes unchecked during library development. Thus, validating these cells exhaustively prior to customer delivery is highly advantageous to not only improve customer satisfaction but also to reduce design costs. We address this challenge by presenting a methodology to validate the power management and data retention cells that are used in the logical design flow of low-power chips. For a quick adoption by standard cell library design teams, the framework is fully automated and runs out-of-the-box. The proposed framework has been implemented and deployed within the Samsung Foundry ecosystem to enhance the overall quality of library design kit deliverables.

翻译：标准单元库的开发涉及在多种单元级抽象层次上对大量门级电路进行特性表征。验证这些单元的行为在很大程度上依赖于电路设计人员的手动技能。电源管理与数据保持单元尤其具有挑战性，除了逻辑功能外，还必须对其电压和电源配置进行全面检查。此外，当标准单元被提取为多种模型时，这些模型间的不一致性通常在库开发过程中未被检测。因此，在交付客户前对这些单元进行详尽验证，不仅有利于提高客户满意度，还能降低设计成本。我们通过提出一种验证方法来解决这一挑战，该方法用于验证低功耗芯片逻辑设计流程中使用的电源管理与数据保持单元。为便于标准单元库设计团队快速采用，该框架完全自动化且可开箱即用。所提出的框架已在三星代工生态系统内实施部署，以提升库设计套件交付成果的整体质量。