In digital IC design, compared with post-synthesis netlists or layouts, the early register-transfer level (RTL) stage offers greater optimization flexibility for both designers and EDA tools. However, timing information is typically unavailable at this early stage. Some recent machine learning (ML) solutions propose to predict the total negative slack (TNS) and worst negative slack (WNS) of an entire design at the RTL stage, but the fine-grained timing information of individual registers remains unavailable. In this work, we address the unique challenges of RTL timing prediction and introduce our solution named RTL-Timer. To the best of our knowledge, this is the first fine-grained general timing estimator applicable to any given design. RTL-Timer explores multiple promising RTL representations and proposes customized loss functions to capture the maximum arrival time at register endpoints. RTL-Timer's fine-grained predictions are further applied to guide optimization in a standard synthesis flow. The average results on unknown test designs demonstrate a correlation above 0.89, contributing around 3% WNS and 10% TNS improvement after optimization.

翻译：在数字集成电路设计中，与综合后的网表或版图相比，早期的寄存器传输级（RTL）阶段为设计人员和 EDA 工具提供了更大的优化灵活性。然而，时序信息在这一早期阶段通常不可用。近期的一些机器学习（ML）解决方案提出在 RTL 阶段预测整个设计的总负松弛度（TNS）和最差负松弛度（WNS），但单个寄存器级别的细粒度时序信息仍然不可获取。在本工作中，我们应对 RTL 时序预测的独特挑战，并介绍我们的解决方案 RTL-Timer。据我们所知，这是首个适用于任意给定设计的细粒度通用时序估计器。RTL-Timer 探索了多种有前景的 RTL 表示方法，并提出定制化的损失函数以捕获寄存器端点的最大到达时间。RTL-Timer 的细粒度预测进一步用于指导标准综合流程中的优化。在未知测试设计上的平均结果表明，相关性超过 0.89，优化后 WNS 改善约 3%，TNS 改善约 10%。