Layout synthesis is mapping a quantum circuit to a quantum processor. SWAP gate insertions are needed for scheduling 2-qubit gates only on connected physical qubits. With the ever-increasing number of qubits in NISQ processors, scalable layout synthesis is of utmost importance. With large optimality gaps observed in heuristic approaches, scalable exact methods are needed. While recent exact and near-optimal approaches scale to moderate circuits, large deep circuits are still out of scope. In this work, we propose a SAT encoding based on parallel plans that apply 1 SWAP and a group of CNOTs at each time step. Using domain-specific information, we maintain optimality in parallel plans while scaling to large and deep circuits. From our results, we show the scalability of our approach which significantly outperforms leading exact and near-optimal approaches (up to 100x). For the first time, we can optimally map several 8, 14, and 16 qubit circuits onto 54, 80, and 127 qubit platforms with up to 17 SWAPs. While adding optimal SWAPs, we also report near-optimal depth in our mapped circuits.

翻译：布局综合是将量子电路映射到量子处理器的过程。为实现仅能在相连物理量子比特上执行的二量子比特门调度，需要插入SWAP门。随着NISQ处理器中量子比特数量的持续增长，可扩展的布局综合方法变得至关重要。鉴于启发式方法存在显著的最优性差距，需要可扩展的精确方法。虽然近期的精确及近似最优方法已能扩展到中等规模电路，但大规模深度电路仍超出其处理范围。本研究提出一种基于并行规划的SAT编码方法，其在每个时间步同时执行1个SWAP门和一组CNOT门。通过利用领域特定信息，我们在扩展到大规模深度电路的同时，保持了并行规划方案的最优性。实验结果表明，我们的方法具有卓越的可扩展性，其性能显著优于主流的精确及近似最优方法（最高可达100倍）。我们首次实现了将多个8、14和16量子比特电路以最优方式映射到54、80和127量子比特平台，最多仅需17个SWAP门。在实现最优SWAP门插入的同时，我们获得的映射电路深度也达到近似最优水平。