Dynamic GNN inference has exhibited effectiveness in High Energy Physics (HEP) experiments at High Luminosity Large Hadron Collider (HL-LHC) due to strong capability to model complex particle interactions in collision events. Future HEP experiments will involve detectors that produce 10x more collision data to help unlocking physics discoveries. Due to limitations in offline compute capacity and storage, revamped trigger systems require FPGAs to run ultra-low-latency Machine Learning models for online filtering of useful events with low power consumption. State-of-the-art GNN accelerators relied on static graph structures, but this assumption breaks down in real-time HL-LHC trigger systems and edge-based dynamic GNN models where edge embeddings change in-place based on neighbor node embeddings at runtime. We propose DGNNFlow, a novel dataflow architecture for real-time edge-based dynamic GNN inference applications, especially HL-LHC trigger systems, with three key contributions. First, we introduce hardware support for dynamic computation of edge embeddings. Second, we resolve data dependencies in edge-based dynamic GNN dataflow, where edge embedding is formulated using its source and target nodes. Third, we perform input dynamic graph construction auxiliary setup for complete support of models without pre-defined edge embeddings. We deployed DGNNFlow using AMD Alveo U50 FPGA to evaluate end-to-end latency on-board at 200 MHz clock frequency. DGNNFlow achieved 1.6x-6.3x speedup and 0.22x power consumption compared to GPU (NVIDIA RTX A6000) with batch sizes from 1 to 4, 3.2x-5.1x speedup and 0.25x power consumption compared to CPU (Intel Xeon Gold 6226R). Our complete implementation is publicly available on GitHub.

翻译：在大型强子对撞机高亮度运行（HL-LHC）的高能物理实验中，动态图神经网络推理因能够有效建模对撞事件中复杂的粒子相互作用而展现出显著效果。未来高能物理实验所涉及的探测器将产生10倍于当前的对撞数据，这有助于解锁新的物理学发现。受限于离线计算能力与存储容量，升级后的触发系统需采用现场可编程门阵列（FPGA）运行超低延迟的机器学习模型，以低功耗在线筛选有效物理事件。现有最先进的图神经网络加速器依赖于静态图结构，但在实时HL-LHC触发系统及基于边缘的动态图神经网络模型中，这一前提不再成立——因为边缘嵌入会在运行时根据邻域节点的嵌入进行原位更新。我们提出DGNNFlow，一种面向实时边缘动态图神经网络推理应用（特别是HL-LHC触发系统）的新型数据流架构，包含三项核心贡献：首先，引入支持边缘嵌入动态计算的硬件机制；其次，解决边缘动态图神经网络数据流中因边缘嵌入由源节点与目标节点共同定义而产生的数据依赖问题；第三，通过输入动态图构建的辅助设置，实现对未预定义边缘嵌入模型的完整支持。我们在AMD Alveo U50 FPGA上部署DGNNFlow，以200 MHz时钟频率评估板级端到端延迟。实验结果表明，在批处理大小为1至4的范围内，与GPU（NVIDIA RTX A6000）相比，DGNNFlow实现1.6倍至6.3倍加速及0.22倍功耗；与CPU（Intel Xeon Gold 6226R）相比，实现3.2倍至5.1倍加速及0.25倍功耗。完整实现代码已开源至GitHub。