Architectural simulators hold a vital role in RISC-V research, providing a crucial platform for workload evaluation without the need for costly physical prototypes. They serve as a dynamic environment for exploring innovative architectural concepts, enabling swift iteration and thorough analysis of performance metrics. As deep learning algorithms become increasingly pervasive, it is essential to benchmark new architectures with machine learning workloads. The diverse computational kernels used in deep learning algorithms highlight the necessity for a comprehensive compilation toolchain to map to target hardware platforms. This study evaluates the performance of a wide array of machine learning workloads on RISC-V architectures using gem5, an open-source architectural simulator. Leveraging an open-source compilation toolchain based on Multi-Level Intermediate Representation (MLIR), the research presents benchmarking results specifically focused on deep learning inference workloads. Additionally, the study sheds light on current limitations of gem5 when simulating RISC-V architectures, offering insights for future development and refinement.

翻译：架构模拟器在RISC-V研究中具有至关重要的作用，为工作负载评估提供了关键平台，无需昂贵的物理原型。它们作为探索创新架构概念的动态环境，能够快速迭代并深入分析性能指标。随着深度学习算法日益普及，使用机器学习工作负载对新架构进行基准测试显得尤为重要。深度学习算法中多样化的计算内核凸显了需要完备编译工具链以映射至目标硬件平台的必要性。本研究利用开源架构模拟器gem5，评估了RISC-V架构上多种机器学习工作负载的性能。通过采用基于多级中间表示（MLIR）的开源编译工具链，本研究呈现了专门针对深度学习推理工作负载的基准测试结果。此外，本研究揭示了gem5在模拟RISC-V架构时存在的当前局限性，为未来的开发与完善提供了见解。