As RISC-V adoption accelerates, domains such as automotive, the Internet of Things (IoT), and industrial control are attracting growing attention. These domains are subject to stringent Size, Weight, Power, and Cost (SWaP-C) constraints, which have driven a shift toward heterogeneous Systems-on-Chip (SoCs) integrating general-purpose CPUs, tightly coupled accelerators, and diverse I/O devices with different integrity levels. While such integration improves cost efficiency and performance, it introduces a fundamental safety and security challenge: enforcing system-level isolation in mixed-criticality environments. Although RISC-V International has proposed several hardware isolation primitives, including RISC-V Worlds, IOPMP, and SmMTT, their interoperability, scalability, and suitability for real-time systems remain insufficiently understood. In this paper, we present a comparative analysis of these primitives from the perspective of practical heterogeneous SoC designs. We implement an IOPMP, a World-based checker, and a modified RISC-V World checker that addresses key limitations of the baseline specification, and evaluate their trade-offs in terms of security guarantees and power-performance-area (PPA). Our results show that the World-based checker introduces a fixed, configuration-independent access latency, achieving lower worst-case delay than the evaluated alternatives while scaling predictably with system size. At the macro level, we estimate that the proposed modifications reduce SoC area by up to approximately 5% compared to a baseline design. All artifacts will be released as open source, and we expect these findings to directly contribute to the evolution and ratification of RISC-V specifications, as well as to the design of future RISC-V SoCs.

翻译：随着RISC-V生态的加速发展，汽车电子、物联网和工业控制等领域对其关注度日益提升。这些领域受到严格的尺寸、重量、功耗和成本约束，推动着系统设计向异构片上系统方向演进——即集成通用CPU、紧耦合加速器以及具有不同完整性等级的多类I/O设备。尽管这种集成方式提升了成本效益与性能，却带来了根本性的安全挑战：如何在混合关键性环境中实现系统级隔离。虽然RISC-V国际联盟已提出多种硬件隔离原语（包括RISC-V Worlds、IOPMP和SmMTT），但其互操作性、可扩展性及对实时系统的适用性仍未得到充分理解。本文从实际异构SoC设计的角度出发，对这些隔离原语进行了比较分析。我们实现了IOPMP模块、基于World的检查器，以及针对基准规范关键缺陷改进的RISC-V World检查器，并从安全保证与功耗-性能-面积三个维度评估了其设计权衡。实验结果表明：基于World的检查器具有固定且与配置无关的访问延迟，在系统规模可预测扩展的前提下，其最坏情况延迟低于其他对比方案。在宏观层面，估算显示改进方案可使SoC面积较基准设计减少约5%。所有实现成果将以开源形式发布，我们期望这些发现能直接推动RISC-V规范的演进完善与标准确立，并为未来RISC-V SoC设计提供参考。