With the rise of Deep Learning (DL), our world braces for AI in every edge device, creating an urgent need for edge-AI SoCs. This SoC hardware needs to support high throughput, reliable and secure AI processing at Ultra Low Power (ULP), with a very short time to market. With its strong legacy in edge solutions and open processing platforms, the EU is well-positioned to become a leader in this SoC market. However, this requires AI edge processing to become at least 100 times more energy-efficient, while offering sufficient flexibility and scalability to deal with AI as a fast-moving target. Since the design space of these complex SoCs is huge, advanced tooling is needed to make their design tractable. The CONVOLVE project (currently in Inital stage) addresses these roadblocks. It takes a holistic approach with innovations at all levels of the design hierarchy. Starting with an overview of SOTA DL processing support and our project methodology, this paper presents 8 important design choices largely impacting the energy efficiency and flexibility of DL hardware. Finding good solutions is key to making smart-edge computing a reality.

翻译：随着深度学习（DL）的兴起，全球正迎来边缘设备中无处不在的AI应用，这催生了对边缘AI系统级芯片（SoC）的迫切需求。此类SoC硬件需支持高吞吐量、可靠且安全的AI处理，同时实现超低功耗（ULP）和极短的市场投放时间。凭借在边缘解决方案和开放处理平台领域的深厚积淀，欧盟在引领这一SoC市场方面具有得天独厚的优势。然而，这要求AI边缘处理的能效至少提升100倍，同时具备足够的灵活性和可扩展性，以应对AI这一快速演进的技术目标。由于这类复杂SoC的设计空间极为庞大，需要先进的工具来确保其设计的可行性。CONVOLVE项目（目前处于初始阶段）正是针对这些障碍而提出。该项目采用整体性方法，在设计的各个层级进行创新。本文首先概述了当前最先进的DL处理支持技术及我们的项目方法，随后提出了8个对DL硬件能效与灵活性具有重大影响的关键设计选择。找到优良的解决方案，是实现智能边缘计算落地的关键所在。