Achieving high compute utilization across a wide range of AI workloads is crucial for the efficiency of versatile DNN accelerators. This paper presents the Voltra chip and its utilization-optimised DNN accelerator architecture, which leverages 3-Dimensional (3D) spatial data reuse along with efficient and flexible shared memory access. The 3D spatial dataflow enables balanced spatial data reuse across three dimensions, improving spatial utilization by up to 2.0x compared to a conventional 2D design. Inside the shared memory access architecture, Voltra incorporates flexible data streamers that enable mixed-grained hardware data pre-fetching and dynamic memory allocation, further improving the temporal utilization by 2.12-2.94x and achieving 1.15-2.36x total latency speedup compared with the non-prefetching and separated memory architecture, respectively. Fabricated in 16nm technology, our chip achieves 1.60 TOPS/W peak system energy efficiency and 1.25 TOPS/mm2 system area efficiency, which is competitive with state-of-the-art solutions while achieving high utilization across diverse workloads.

翻译：在多样化的AI工作负载上实现高计算利用率对于通用DNN加速器的效率至关重要。本文介绍了Voltra芯片及其利用率优化的DNN加速器架构，该架构利用了三维空间数据复用以及高效灵活的共享内存访问。三维空间数据流实现了三个维度上均衡的空间数据复用，与传统二维设计相比，空间利用率最高可提升2.0倍。在共享内存访问架构内部，Voltra集成了灵活的数据流控制器，支持混合粒度的硬件数据预取和动态内存分配，与非预取及分离式内存架构相比，时间利用率进一步提升了2.12-2.94倍，并实现了1.15-2.36倍的总延迟加速。该芯片采用16纳米工艺制造，实现了1.60 TOPS/W的峰值系统能效和1.25 TOPS/mm²的系统面积效率，在与最先进解决方案竞争的同时，在多样化工作负载上实现了高利用率。