The increasing complexity of modern processor and IP designs presents significant challenges in identifying and mitigating hardware flaws early in the IC design cycle. Traditional hardware fuzzing techniques, inspired by software testing, have shown promise but face scalability issues, especially at the gate-level netlist where bugs introduced during synthesis are often missed by RTL-level verification due to longer simulation times. To address this, we introduce GraphFuzz, a graph-based hardware fuzzer designed for gate-level netlist verification. In this approach, hardware designs are modeled as graph nodes, with gate behaviors encoded as features. By leveraging graph learning algorithms, GraphFuzz efficiently detects hardware vulnerabilities by analyzing node patterns. Our evaluation across benchmark circuits and open-source processors demonstrates an average prediction accuracy of 80% and bug detection accuracy of 70%, highlighting the potential of graph-based methods for enhancing hardware verification.

翻译：现代处理器与IP设计的日益复杂性，为在集成电路设计周期早期识别与缓解硬件缺陷带来了严峻挑战。受软件测试启发的传统硬件模糊测试技术虽展现出潜力，但面临可扩展性问题，尤其在门级网表层面——由于仿真时间较长，综合阶段引入的漏洞常被RTL级验证所遗漏。为此，我们提出GraphFuzz，一种面向门级网表验证的基于图的硬件模糊测试器。该方法将硬件设计建模为图节点，并将门级行为编码为特征。通过运用图学习算法，GraphFuzz能高效分析节点模式以检测硬件漏洞。我们在基准电路与开源处理器上的评估表明，其平均预测准确率达80%，漏洞检测准确率达70%，彰显了基于图的方法在增强硬件验证方面的潜力。