Analog to Digital Converters (ADCs) are a major contributor to the power consumption of multiple-input multiple-output (MIMO) receivers with large antenna arrays operating in the millimeter wave carrier frequencies. This is especially the case in large bandwidth communication systems, due to the sudden drop in energy-efficiency of ADCs as the sampling rate is increased above 100MHz. Two mitigating energy-efficient approaches which have received significant recent interest are i) to reduce the number of ADCs via analog and hybrid beamforming architectures, and ii) to reduce the resolution of the ADCs which in turn decreases power consumption. However, decreasing the number and resolution of ADCs leads to performance loss -- in terms of achievable rates -- due to increased quantization error. In this work, we study the application of practically implementable nonlinear analog operators such as envelope detectors and polynomial operators, prior to sampling and quantization at the ADCs, as a way to mitigate the aforementioned rate-loss. A receiver architecture consisting of linear analog combiners, nonlinear analog operators, and few-bit ADCs is designed. The fundamental information theoretic performance limits of the resulting communication system, in terms of achievable rates, are investigated under various assumptions on the set of implementable analog operators. Extensive numerical evaluations and simulations of the communication system are provided to compare the set of achievable rates under different architecture designs and parameters. Circuit simulations and measurement results, based on both 22 nm FDSOI CMOS technology and 65 nm Bulk CMOS transistor technologies, are provided to justify the power efficiency of the proposed receiver architecture deploying envelope detectors and polynomial operators.

翻译：模数转换器（ADC）是工作于毫米波载波频段、具有大规模天线阵列的多输入多输出（MIMO）接收机功耗的主要来源。特别是在大带宽通信系统中，当采样率提升至100MHz以上时，ADC的能效会急剧下降。近年来，两种具有高能效潜力的缓解方案备受关注：一是通过模拟和混合波束赋形架构减少ADC数量，二是降低ADC分辨率以降低功耗。然而，减少ADC数量与分辨率会因量化误差增大而导致性能损失（即可达速率下降）。本文研究在ADC采样与量化之前应用可实现的实际非线性模拟算子（如包络检波器和多项式算子）来缓解上述速率损失的方法。我们设计了一种由线性模拟合路器、非线性模拟算子及少比特ADC构成的接收机架构。在可实现的模拟算子集合的不同假设条件下，研究了该通信系统在可达速率方面的基础信息论性能极限。通过大量数值评估与通信系统仿真，比较了不同架构设计与参数下的可达速率集合。基于22nm FDSOI CMOS技术和65nm Bulk CMOS晶体管技术的电路仿真与测量结果，验证了采用包络检波器和多项式算子的接收机架构的功率效率。