Analog in-memory computing (AiMC) is an emerging technology that shows fantastic performance superiority for neural network acceleration. However, as the computational bit-width and scale increase, high-precision data conversion and long-distance data routing will result in unacceptable energy and latency overheads in the AiMC system. In this work, we focus on the potential of in-charge computing and in-time interconnection and show an innovative AiMC architecture, named AiDAC, with three key contributions: (1) AiDAC enhances multibit computing efficiency and reduces data conversion times by grouping capacitors technology; (2) AiDAC first adopts row drivers and column time accumulators to achieve large-scale AiMC arrays integration while minimizing the energy cost of data movements. (3) AiDAC is the first work to support large-scale all-analog multibit vector-matrix multiplication (VMM) operations. The evaluation shows that AiDAC maintains high-precision calculation (less than 0.79% total computing error) while also possessing excellent performance features, such as high parallelism (up to 26.2TOPS), low latency (<20ns/VMM), and high energy efficiency (123.8TOPS/W), for 8bits VMM with 1024 input channels.

翻译：模拟存内计算（AiMC）是一种新兴技术，在神经网络加速方面展现出卓越的性能优势。然而，随着计算位宽和规模的增加，高精度数据转换和长距离数据路由将导致AiMC系统产生不可接受的能量和延迟开销。本文聚焦于电荷内计算与即时互连的潜力，提出了一种创新的AiMC架构——AiDAC，其核心贡献包括三点：（1）AiDAC通过电容分组技术提升多比特计算效率，减少数据转换次数；（2）AiDAC首次采用行驱动器和列时间累加器，在最小化数据移动能量消耗的同时实现大规模AiMC阵列集成；（3）AiDAC是首个支持大规模全模拟多比特向量矩阵乘法（VMM）运算的工作。评估表明，在1024输入通道的8比特VMM任务中，AiDAC不仅保持高精度计算（总计算误差低于0.79%），还具备卓越的性能特征：高并行度（高达26.2TOPS）、低延迟（<20ns/VMM）和高能效（123.8TOPS/W）。