Spiking Neural Networks (SNNs) are bio-plausible models that hold great potential for realizing energy-efficient implementations of sequential tasks on resource-constrained edge devices. However, commercial edge platforms based on standard GPUs are not optimized to deploy SNNs, resulting in high energy and latency. While analog In-Memory Computing (IMC) platforms can serve as energy-efficient inference engines, they are accursed by the immense energy, latency, and area requirements of high-precision ADCs (HP-ADC), overshadowing the benefits of in-memory computations. We propose a hardware/software co-design methodology to deploy SNNs into an ADC-Less IMC architecture using sense-amplifiers as 1-bit ADCs replacing conventional HP-ADCs and alleviating the above issues. Our proposed framework incurs minimal accuracy degradation by performing hardware-aware training and is able to scale beyond simple image classification tasks to more complex sequential regression tasks. Experiments on complex tasks of optical flow estimation and gesture recognition show that progressively increasing the hardware awareness during SNN training allows the model to adapt and learn the errors due to the non-idealities associated with ADC-Less IMC. Also, the proposed ADC-Less IMC offers significant energy and latency improvements, $2-7\times$ and $8.9-24.6\times$, respectively, depending on the SNN model and the workload, compared to HP-ADC IMC.

翻译：脉冲神经网络（SNNs）是具有生物合理性的模型，在资源受限的边缘设备上实现顺序任务的能效执行方面潜力巨大。然而，基于标准GPU的商业边缘平台并非为部署SNNs而优化，导致高能耗和高延迟。尽管模拟存内计算（IMC）平台可作为能效推理引擎，但其受困于高精度模数转换器（HP-ADC）对能耗、延迟和面积的巨大需求，这掩盖了存内计算的优势。我们提出一种硬件/软件协同设计方法，将SNNs部署到无模数转换器（ADC-Less）的IMC架构中，采用灵敏放大器作为1比特ADC替代传统HP-ADC，从而缓解上述问题。所提框架通过进行硬件感知训练，将精度损失降至最低，并能从简单的图像分类任务扩展到更复杂的顺序回归任务。在光流估计和手势识别等复杂任务上的实验表明，在SNN训练过程中逐步增强硬件感知能力，可使模型适应并学习因无ADC-IMC非理想性带来的误差。此外，与HP-ADC IMC相比，所提出的无ADC-IMC在能耗和延迟方面分别实现了2-7倍和8.9-24.6倍的显著提升，具体提升幅度取决于SNN模型和工作负载。