To accommodate the growing memory footprints of today's applications, CPU vendors have employed large DRAM caches, backed by large non-volatile memories like Intel Optane (e.g., Intel's Cascade Lake). The existing computer architecture simulators do not provide support to model and evaluate systems which use DRAM devices as a cache to the non-volatile main memory. In this work, we present a cycle-level DRAM cache model which is integrated with gem5. This model leverages the flexibility of gem5's memory devices models and full system support to enable exploration of many different DRAM cache designs. We demonstrate the usefulness of this new tool by exploring the design space of a DRAM cache controller through several case studies including the impact of scheduling policies, required buffering, combining different memory technologies (e.g., HBM, DDR3/4/5, 3DXPoint, High latency) as the cache and main memory, and the effect of wear-leveling when DRAM cache is backed by NVM main memory. We also perform experiments with real workloads in full-system simulations to validate the proposed model and show the sensitivity of these workloads to the DRAM cache sizes.

翻译：为适应当今应用程序不断增长的内存占用量，CPU供应商采用了大型DRAM缓存，支持大型非易失性存储器，如Intel Optane（例如，Intel的Cascade Lake）。现有的计算机架构模拟器不提供支持，用作缓存以非易失性主存储器的DRAM设备的系统建模和评估。在这项工作中，我们介绍了一个基于周期的DRAM缓存模型，并将其与gem5集成。该模型利用了gem5内存设备模型和系统支持的灵活性，以便探索许多不同的DRAM缓存设计。通过多个案例研究，包括调度策略的影响，所需的缓冲区，将不同的内存技术（例如HBM，DDR3/4/5，3DXPoint，高延迟）组合作为缓存和主要存储器以及在DRAM缓存由NVM主存储器支持时的磨损平衡的影响，我们展示了这个新工具的有用性。我们还通过完整系统模拟实验对真实工作负载进行了实验，以验证所提出的模型，并展示这些工作负载对DRAM缓存大小的敏感性。