To accommodate the growing memory footprints of today's applications, CPU vendors have employed large DRAM caches, backed by large non-volatile memories like Intel Optane (e.g., Intel's Cascade Lake). The existing computer architecture simulators do not provide support to model and evaluate systems which use DRAM devices as a cache to the non-volatile main memory. In this work, we present a cycle-level DRAM cache model which is integrated with gem5. This model leverages the flexibility of gem5's memory devices models and full system support to enable exploration of many different DRAM cache designs. We demonstrate the usefulness of this new tool by exploring the design space of a DRAM cache controller through several case studies including the impact of scheduling policies, required buffering, combining different memory technologies (e.g., HBM, DDR3/4/5, 3DXPoint, High latency) as the cache and main memory, and the effect of wear-leveling when DRAM cache is backed by NVM main memory. We also perform experiments with real workloads in full-system simulations to validate the proposed model and show the sensitivity of these workloads to the DRAM cache sizes.

翻译：为应对现代应用程序日益增长的内存需求，CPU厂商已采用大容量DRAM缓存，并由英特尔Optane等大容量非易失性内存（如英特尔Cascade Lake）提供支持。现有计算机架构模拟器不支持对使用DRAM设备作为非易失性主内存缓存的系统进行建模与评估。在本工作中，我们提出一种集成于gem5的周期级DRAM缓存模型。该模型利用gem5内存设备模型的灵活性与全系统支持能力，可探索多种不同的DRAM缓存设计方案。通过多项案例研究（包括调度策略影响、所需缓冲容量、不同内存技术（如HBM、DDR3/4/5、3DXPoint、高延迟）作为缓存与主内存的组合方式，以及DRAM缓存由NVM主内存支持时的磨损均衡效应），我们展示了这一新工具在探索DRAM缓存控制器设计空间中的实用性。此外，我们通过全系统模拟中的实际工作负载实验验证了所提模型，并展示了这些工作负载对DRAM缓存大小的敏感性。