Whether stemming from malicious intent or natural occurrences, faults and errors can significantly undermine the reliability of any architecture. In response to this challenge, fault detection assumes a pivotal role in ensuring the secure deployment of cryptosystems. Even when a cryptosystem boasts mathematical security, its practical implementation may remain susceptible to exploitation through side-channel attacks. In this paper, we propose a lightweight fault detection architecture tailored for modular exponentiation, a building block of numerous cryptographic applications spanning from classical cryptography to post quantum cryptography. Based on our simulation and implementation results on ARM Cortex-A72 processor, and AMD/Xilinx Zynq Ultrascale+, and Artix-7 FPGAs, our approach achieves an error detection rate close to 100%, all while introducing a modest computational overhead of approximately 7% and area overhead of less than 1% compared to the unprotected architecture. To the best of our knowledge, such an approach benchmarked on ARM processor and FPGA has not been proposed and assessed to date.

翻译：无论是源于恶意攻击还是自然发生，故障和错误都可能显著削弱任何架构的可靠性。为应对这一挑战，故障检测在确保密码系统安全部署中扮演着关键角色。即便密码系统具备数学安全性，其实际实现仍可能因侧信道攻击而受到利用。本文提出了一种轻量级故障检测架构，专为模块化幂运算设计——该运算是从经典密码学到后量子密码学的众多密码应用的基础构建模块。基于在ARM Cortex-A72处理器及AMD/Xilinx Zynq Ultrascale+、Artix-7 FPGA上的仿真与实现结果，我们的方法实现了接近100%的错误检测率，同时相较于未防护架构仅引入约7%的计算开销和低于1%的面积开销。据我们所知，目前尚未有研究提出并评估过这种在ARM处理器和FPGA上进行基准测试的方案。