One of the key challenges when operating microcontrollers in harsh environments such as space is radiation-induced Single Event Upsets (SEUs), which can lead to errors in computation. Common countermeasures rely on proprietary radiation-hardened technologies, low density technologies, or extensive replication, leading to high costs and low performance and efficiency. To combat this, we present Trikarenos, a fault-tolerant 32-bit RISC-V microcontroller SoC in an advanced TSMC 28nm technology. Trikarenos alleviates the replication cost by employing a configurable triple-core lockstep configuration, allowing three Ibex cores to execute applications reliably, operating on ECC-protected memory. If reliability is not needed for a given application, the cores can operate independently in parallel for higher performance and efficiency. Trikarenos consumes 15.7mW at 250MHz executing a fault-tolerant matrix-matrix multiplication, a 21.5x efficiency gain over state-of-the-art, and performance is increased by 2.96x when reliability is not needed for processing, with a 2.36x increase in energy efficiency.

翻译：在太空等恶劣环境中运行微控制器面临的关键挑战之一是辐射引起的单粒子翻转（SEU），这可能导致计算错误。常见的应对措施依赖专有的抗辐射加固技术、低密度工艺或大量冗余设计，导致成本高昂且性能及效率低下。为解决这一问题，我们提出了Trikarenos——一种采用先进台积电28nm工艺制造的容错32位RISC-V微控制器片上系统（SoC）。Trikarenos通过采用可配置的三核锁步架构来降低冗余成本，使三个Ibex内核能够在ECC保护的内存上可靠执行应用。当特定应用无需高可靠性时，这些内核可独立并行运行，以提升性能与效率。在执行容错矩阵乘法运算时，Trikarenos在250MHz频率下功耗为15.7mW，能效较现有最优方案提升21.5倍；当处理任务无需可靠性保障时，性能提升2.96倍，能效提高2.36倍。