General-purpose processors feature a limited number of instructions based on an instruction set. They can be numerous, such as with vector extensions that include hundreds or thousands of instructions, but this comes at a cost; they are often unable to express arbitrary tasks efficiently. This paper explores the concept of having reconfigurable instructions by incorporating reconfigurable areas in a softcore. It follows a relatively new computing paradigm for seamlessly loading instruction implementation-carrying bitstreams from main memory. The resulting softcore is entirely evaluated on an FPGA, essentially having an FPGA-on-FPGA for the instruction implementations, with no notable operating frequency overhead. This is achieved with a custom FPGA architecture called LUTstruction, which is tailored towards low-latency for custom instructions and wide reconfiguration, as well as a soft implementation for the purposes of architectural exploration. All code is open-source to foster further research on reconfigurable instructions.

翻译：通用处理器基于指令集提供有限数量的指令。尽管通过包含成百上千条指令的向量扩展等方式可增加指令数量，但代价高昂——它们往往无法高效表达任意任务。本文探索了通过在软核中集成可重构区域来实现可重构指令的概念。该方法遵循一种相对较新的计算范式，可从主存无缝加载携带指令实现的比特流。所生成的软核完全在FPGA上评估，本质上通过"FPGA上的FPGA"实现指令执行，且无显著工作频率开销。这一成果通过名为LUTstruction的定制FPGA架构实现，该架构针对定制指令的低延迟与宽重构性进行了优化，并提供了用于架构探索的软实现方案。所有代码均已开源，以促进可重构指令领域的进一步研究。