Designing a system-on-chip (SoC) for deep neural network (DNN) acceleration requires balancing multiple metrics such as latency, power, and area. However, most existing methods ignore the interactions among different SoC components and rely on inaccurate and error-prone evaluation tools, leading to inferior SoC design. In this paper, we present SoC-Tuner, a DNN-targeting exploration framework to find the Pareto optimal set of SoC configurations efficiently. Our framework constructs a thorough SoC design space of all components and divides the exploration into three phases. We propose an importance-based analysis to prune the design space, a sampling algorithm to select the most representative initialization points, and an information-guided multi-objective optimization method to balance multiple design metrics of SoC design. We validate our framework with the actual very-large-scale-integration (VLSI) flow on various DNN benchmarks and show that it outperforms previous methods. To the best of our knowledge, this is the first work to construct an exploration framework of SoCs for DNN acceleration.

翻译：设计用于深度神经网络加速的系统级芯片需平衡延迟、功耗与面积等多个指标。然而，现有方法大多忽略芯片各组件间的相互作用，且依赖不准确、易出错的评估工具，导致芯片设计质量低下。本文提出面向DNN的探索框架SoC-Tuner，可高效寻找帕累托最优的芯片配置集合。该框架构建包含所有组件的完整芯片设计空间，并将探索过程分为三个阶段。我们提出基于重要性分析的空间剪枝方法、最具代表性初始化点的采样算法，以及信息引导的多目标优化方法用以平衡芯片设计的多个指标。通过实际超大规模集成电路流程在多种DNN基准上的验证，本框架性能优于现有方法。据我们所知，这是首个面向DNN加速芯片的探索框架。