Resistive Random Access Memory (RRAM) crossbar arrays are an attractive memory structure for emerging nonvolatile memory due to their high density and excellent scalability. Their ability to perform logic operations using RRAM devices makes them a critical component in non-von Neumann processing-in-memory architectures. Passive RRAM crossbar arrays (1-RRAM or 1R), however, suffer from a major issue of sneak path currents, leading to a lower readout margin and increasing write failures. To address this challenge, active RRAM arrays have been proposed, which incorporate a selector device in each memory cell (termed 1-selector-1-RRAM or 1S1R). The selector eliminates currents from unselected cells and therefore effectively mitigates the sneak path phenomenon. Yet, there is a need for a comprehensive analysis of 1S1R arrays, particularly concerning in-memory computation. In this paper, we introduce a 1S1R model tailored to a VO2-based selector and TiN/TiOx/HfOx/Pt RRAM device. We also present simulations of 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from $4\times4$ to $512\times512$. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.

翻译：阻变随机存取存储器（RRAM）交叉阵列因其高密度和优异的可扩展性，成为新兴非易失性存储器中极具吸引力的存储结构。其利用RRAM器件执行逻辑运算的能力，使其成为非冯·诺依曼存内计算架构中的关键组件。然而，无源RRAM交叉阵列（1R结构）存在严重的潜行路径电流问题，导致读取裕度降低并增加写入失败。为应对这一挑战，有源RRAM阵列被提出，其在每个存储单元中集成选通器件（称为1S1R结构）。该选通器可消除未选中单元的电流，从而有效抑制潜行路径现象。但目前仍需对1S1R阵列进行全面分析，特别是在存内计算方面。本文提出了一种针对VO₂基选通器和TiN/TiOx/HfOx/Pt RRAM器件定制的1S1R模型，并完成了涵盖$4\times4$至$512\times512$多种阵列尺寸、包含所有寄生参数的1S1R阵列仿真。我们通过开关延迟、功耗和读取裕度评估了忆阻器辅助逻辑（MAGIC）门的性能，并与无源1R阵列进行了对比分析。